1. Field of the Invention
The disclosure herein is directed to a temperature detecting circuit, and more particularly, to a temperature detecting circuit capable of more precisely detecting the operation temperature of a semiconductor device.
2. Description of the Related Art
Semiconductor devices such as dynamic random access memories (DRAMs) refresh data stored in memory cells to continuously maintain the stored data. In the art, this is known as a self-refresh operation. In a self-refresh operation, current flows inside the device, which causes power consumption. There is a need in the art to reduce this power consumption so as to reduce power consumption in the semiconductor devices.
Recently, a semiconductor device was introduced having a temperature detecting circuit with a bandgap reference circuit for changing the self-refresh period depending on the operating temperature of the semiconductor device, thereby minimizing the power consumption caused by the self-refresh current.
FIG. 1 illustrates a conventional temperature detecting circuit having a bandgap reference circuit.
Referring to FIG. 1, the temperature detecting circuit includes a reference voltage generator 1 for generating a reference voltage Vref corresponding to reference current Ir. The temperature detecting circuit further includes a first detection voltage generator 2 for generating a first detection voltage VT1 corresponding to a first detection current I1, a second detection voltage generator 3 for generating a second detection voltage VT2 corresponding to second detection current I2, and a temperature detection signal generator 4 for comparing each of the first and second detection voltages VT1 and VT2 with the reference voltage Vref to generate first and second temperature detection signals T1_sig and T2_sig.
The reference voltage generator 1 includes a first PMOS transistor PM1 having a source to which a power supply voltage VDD is applied, a gate connected to a first node N1, and a drain connected to a second node N2; a second PMOS transistor PM2 having a source to which the power supply voltage VDD is applied, a gate connected to the first node N1, and a drain connected to a third node N3; a first diode D1 connected in series between the second node N2 and a ground voltage GND; a reference resistor Rr and a second diode D2 connected in series between the third node N3 and the ground voltage GND; and a first operational (OP) amplifier OP1 having an output terminal connected to the first node N1, (−) input terminal connected to the second node N2, and a (+) input terminal connected to the third node N3.
The first detection voltage generator 2 includes a third PMOS transistor PM3 having a source to which the power supply voltage VDD is applied, a gate connected to a fourth node N4, and a drain connected to a fifth node N5; a first resistor R1 connected in series between the fifth node N5 and the ground voltage GND; and a second OP amplifier OP2 having an output terminal connected to the fourth node N4, a (+) input terminal connected to the fifth node N5, and an (−) input terminal connected to the third node N3. The second detection voltage generator 3 includes a fourth PMOS transistor PM4 having a source to which the power supply voltage VDD is applied, a gate connected to a sixth node N6 and a drain connected to a seventh node N7; a second resistor R2 connected in series between the seventh node N7 and the ground voltage GND, and a third OP amplifier OP3 having a (+) input terminal connected to the seventh node N7, a (−) input terminal connected to the third node N3, and an output terminal connected to the sixth node N6.
The temperature detection signal generator 4 includes a first comparator COM1 for comparing the reference voltage Vref at the first node N1 with the first detection voltage VT1 at the fourth node N4 to generate the first temperature detection signal T1_sig; and a second comparator COM2 for comparing the reference voltage Vref at the first node N1 with the second detection voltage VT2 at the sixth node N6 to generate the second temperature detection signal T2_sig.
Operation of the conventional temperature detecting circuit will now be described with reference to FIG. 1.
It is assumed that the first and second diodes D1 and D2 are the same type diodes, and W/L (width/length) of the PMOS transistors PM1, PM2, PM3 and PM4 exhibits that PM1:PM2:PM3:PM4=M:1:M:M.
Since current input to the input terminals of the operational amplifiers may be neglected, currents flowing into the second, third, fifth and seventh nodes N2, N3, N5 and N7 are the same as those flowing into the drains of the PMOS transistors PM1, PM2, PM3 and PM4, respectively. Current ratio exhibits N2:N3:N5:N7=M:1:M:M depending on the W/L of the PMOS transistors PM1, PM2, PM3 and PM4.
Current flowing through each turned-on diode may be represented by the following Equation 1:I=Is exp[VD/VT]  Equation 1where Is indicates reverse saturation current of the diode, VD indicates a voltage across the diode, and VT indicates a thermal voltage having a value of (k×T)/q. k indicates constant, T indicates a temperature, and q indicates charge.
Since all voltages at the input terminals of the operational amplifiers are the same, all voltages at the second, third, fifth and seventh nodes N2, N3, N5 and N7 are the same and the following Equation 2 is obtained:V(N2)=V(N3)=Ir×Rr+VD1=VD2,  Equation 2where VD1 indicates a voltage across the first diode D1, and VD2 indicates a voltage across the second diode D2.
Since Io=Is exp[VD2/VT], VD2=VT×ln(Io/Is). Since Ir=Is exp[VD1/VT], VD1=VT×ln((Io/M)/Is). Accordingly, Ir may be represented by the following Equation 3 from Equation 2.Ir=(VT×ln(M))/Rr  Equation 3
It can be seen that Ir is proportional to the temperature and inversely proportional to the resistance.
Further, since all the voltages at the second, third, fifth and seventh nodes N2, N3, N5 and N7 are the same, the voltages at the second, fifth and seventh nodes N2, N5 and N7 are the same as the voltage at the third node N3, and the voltage at the third node N3 is the same as the voltage VD2 across the second diode D2. Thus, the voltage at the third node N3 becomes “VT×ln(Io/Is)”.
Generally, when a temperature is elevated, Is increases at a greater rate compared to the thermal voltage VT of the diode and the voltage across the diode decreases. Accordingly, all of the voltage at the third node N3 and the voltages at the second, fifth and seventh nodes N2, N5 and N7 are reduced. This reduces the first and second detection currents I1 and I2 flowing through the first and second resistors R1 and R2 according to an equation, I=V/R. As a result, it can be seen that the first and second detection currents I1 and I2 are reduced as the temperature is elevated.
The temperature detecting circuit of FIG. 1 is able to detect the operation temperature of the semiconductor device based on the characteristic that, as the temperature is elevated, the reference current Ir increases but the first and second detection currents I1 and I2 decrease, as shown in FIG. 2A.
In this case, the temperature at which the first detection current I1 and the reference current Ir intersect becomes a first set temperature T1, and a temperature at which a second detection current I2 and the reference current Ir intersect becomes a second set temperature T2.
The first, second and third OP amplifiers OP1, OP2 and OP3 output the reference voltage Vref, the first detection voltage VT1, and the second detection voltage VT2 corresponding to the reference current Ir, the first detection current I1, and the second detection current I2 at the first, fourth, and sixth nodes N1, N4 and N6, respectively.
As in FIG. 2B, the first comparator COM1 compares the reference voltage Vref to the first detection voltage VT1 to enable the first temperature detection signal T1_sig when the semiconductor device operates at a temperature higher than the first set temperature T1, and the second comparator COM2 compares the reference voltage Vref to the second detection voltage VT2 to enable the second temperature detection signal T2_sig when the semiconductor device operates at a temperature higher than the second set temperature T2.
The first and second temperature detection signals T1_sig and T2_sig are input to a self-refresh period variable circuit (not shown), which is implemented by for example a counter, to change the self-refresh period of the semiconductor device.
As described above, the conventional temperature detecting circuit detects the operation temperature of the semiconductor device and notifies the self-refresh period variable circuit of the detected operation temperature of the semiconductor device so that the self-refresh period is changed according to the operation temperature of the semiconductor device.
However, the conventional temperature detecting circuit cannot precisely detect operational changes in the temperature of the semiconductor device because the set temperatures are fixed in too great of a temperature detection scale. Accordingly, it is impossible to select and set a self-refresh period that is suitable for the operation temperature of the semiconductor device.
For example, when the first set temperature T1 of the temperature detecting circuit is 10° C., the second set temperature T2 is 50° C., and the operation temperature of the semiconductor device is 45° C., the temperature detecting circuit detects that the semiconductor device operates at a temperature higher than 10° C. to enable only the first temperature detection signal T1_sig. The self-refresh period variable circuit then selects and sets a self-refresh period that is suitable for the semiconductor device operating between 10° C. and 50° C.
However, it is desirable that the actual self-refresh is performed according to a self-refresh period that is suitable for the semiconductor device operating over 45° C. since the operation temperature of the semiconductor device is 45° C.
As described above, with the conventional temperature detecting circuit, it is impossible to precisely select and set a self-fresh period that is suitable for the operation temperature of a semiconductor device. Thus, power consumption caused by self-refresh current may be unnecessarily increased or data stored in memory cells may be lost.